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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

DVCon 2022: Imperas RISC-V Design Verification solutions

DVCon 2022

Abstract:
With a history based in EDA tools and background of SystemVerilog, the Imperas technology is now at the forefront of RISC-V processor verification.
This talk gives an overview of the Imperas solutions for RISC-V verification including examples of the methods used by customers and users on several projects.

Speaker:     Larry Lapides – Imperas Software

The PDF of the slides used in this talk are available at this link

This DVCon presentation can be viewed on the YouTube channel for Imperas here.

Comments

  • Allen Baum, Chair of RISC-V Foundation Technical Committee Task Group for Compliance

    Esperanto Technologies, Inc.

    The work of the RISC-V Compliance Task Group is vital to the success of RISC-V and anyone trying to design or sell RISC-V based products. We welcome the contributions of Imperas and believe that using riscvOVPsim as one of the reference simulators could be highly valuable in the overall compliance effort.

  • Krishna Raghavan, President

    MIPS IP Licensing, Wave Computing

    The Imperas simulation and modeling technology has been a reliable and high-quality testing model used internally by the MIPS engineering team for many years. We are delighted to partner with Imperas to make this industrial-grade simulation technology available to support the MIPS Open program and further the momentum around open hardware development.