Continuous design innovation adds to verification complexity, and pushes more companies to actually do it.
The RISC-V ecosystem is struggling to keep pace with rapid innovation and customization, which is increasing the amount of verification work required for each design and spreading that work out across more engineers at more companies.
The historical assumption is that verification represents 60% to 80% or more of SoC project effort in terms of cost and time for a mature, mainstream processor IP core. But the processor IP business model is based on one-size-fits-all, which allows chip companies to amortize NRE (non-recurring engineering) across many projects. RISC-V implementations tend to be smaller and more customized, and in many cases significantly different from one project to the next.
“A lot of people now have to verify the processor, whereas previously they weren’t,” said Simon Davidmann, CEO of Imperas Software, during a recent panel at the RISC-V Summit. “Verifying a processor, whether it’s the functionality or the performance, is something very new. It used to be done internally in the Intels, the Arms, the Arm architecture licensees, the MIPS, and others. It was all very proprietary and very homegrown. Those companies had huge resources to do it and have done a lot of very smart stuff with internal proprietary solutions that weren’t very public.”…
To read the full Semiconductor Engineering article by Ann Steffora Mutschler, click here.