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Revolutionizing Embedded Software Development

RISC-V Summit 2022: Spotlight - Improving RISC-V Quality with Verification Standards and Advanced Methodologies

RISC-V Summit 2022 Keynote talk

The freedom of RISC-V represents both new innovations in design and also the migration of verification responsibility. This keynote highlights the challenges facing SoC teams as they adopt RISC-V and provides a perspective on how the use of new verification standards and methodologies drives down cost, quality risk, and development time.


Presenter:
Simon Davidmann – Imperas Software Ltd.


The video of this presentation is available on YouTube.


This spotlight talk was also featured in a Breakfast Bytes article by Paul McLellan, available here.

View Document

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Custom Instruction Flow Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Custom Instruction Flow Application Note

Comments

  • Hideki Sugimoto, CTO

    NSITEXE, a group company of DENSO Corporation

    For the automotive market our customers expect the highest standards of quality and design assurance. NSITEXE selected the Imperas Vector Extensions Compliance test cases and RISC-V Reference Model as a foundation for our simulation-based design verification (DV) plans.

  • Simon Davidmann, President and CEO

    Imperas Software

    Having partnered with the Wave Computing MIPS engineering team and IP customers over the past decade, our model and simulation technology has enabled MIPS-based devices to be deployed across a broad range of embedded markets.This no-cost MIPSOpenOVPsim instruction set simulator is an ideal start for developers looking to explore the potential of various SoC designs through Wave Computing’s MIPS Open program.