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Revolutionizing Embedded Software Development

RISC-V Summit 2021 - Demo Theatre SW talk: Porting software to RISC-V using Imperas Virtual Prototypes

Abstract:

While much of the focus and energy of the RISC-V adopters has so far gone into the development of the RISC-V architecture and specific cores, the real success of RISC-V is dependent upon the key software tasks for new applications, porting legacy software, and optimizing OS/RTOS ports and drivers for the wide range of RISC-V devices being built. With more custom silicon projects starting every day, virtual platforms (often called virtual prototypes) offer a viable alternative to hardware prototypes for software engineering tasks. 
This talk will highlight how simulation and virtual prototypes can be used for software development for new processors and SoCs including a demonstration with Quake running on RISC-V.

Co-Author:       Katherine (Kat) Hsu – Imperas Software
Co-Author:       Manny Wright – Imperas Software

The video of this presentation is available at this link.
 

 

View Document

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Nobuyuki Ueyama, President

    eSOL TRINITY Co., Ltd.

    The open ISA of RISC-V is enabling a new wave of processor design innovation across the spectrum of compute requirements in almost all market segments.

    High quality processor verification is not a simple task, but the ease of use and configurable approach with RVVI offered by ImperasDV enables the eSOL TRINITY team to support the expert design teams at NSITEXE and other leading adopters of RISC-V in Japan.

  • Hideki Sugimoto, CTO

    NSITEXE, Inc., a group company of DENSO Corporation

    The NSITEXE Akaria processors, developed with the use of Imperas RISC-V verification technology and the leading-edge SystemVerilog simulator and debug tools from Cadence, are targeted to address the high-performance requirements for AI and automotive requirements. The Akaria processors include the necessary features and quality to achieve the ISO 26262 ASIL D functional safety standard, in addition to being optimized and efficient processors for the next-generation embedded application.

    As the NSITEXE Akaria processors are adopted across a wide range of next-generation automotive, safety-critical, and embedded applications, the verification methodology with the support from Imperas and Cadence has been invaluable in achieving our quality goals and on-time development schedule.