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Imperas at SemIsrael Virtual Technology Week 2020, June 15-17

Imperas at SemIsrael Tech Week 2020 - Virtual Platforms, Development Tools and RISC-V verification reference models

SemIsrael Virtual Technology Week 2020

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation at SemIsrael Virtual Technology Week 2020. Imperas presentation will cover SoC front end design with Architectural Exploration using virtual platforms, and the design flows for RISC-V custom extension and processor verification.

Presentation: “Exploring next generation SoC architectures with Virtual Platforms”

Abstract: As SoC designers explore new architectural approaches with multi-processor configuration and arrays, virtual platforms allow rapid design options and support full application software development to fine tune and test new multi-processor structures with development iterations at the speed of software. RISC-V adds new dimensions of processor flexibility with many options and configurations plus custom instructions. Using software driven design methodologies allows profiling and analysis of new extensions for domain specific applications. The new RISC-V vector extension help support complex arithmetic operations required for applications involving linear algebra, such as supercomputers, cryptography, AI, ML and deep learning (DL). As RISC-V processor are adopted within SoC’s, the full design verification (DV) process can be supported with SystemVerilog test benches and reference model-based verification, including the latest work with Google Instruction Stream Generator, compliance suite, and directed tests. 

When:                  Tuesday June 17, Front-end Design & Verification Track

Virtual Booth:     Imperas staff members also available throughout the conference for on-request demos.

Please email info@imperas.com to request a demo or virtual booth meeting. 

 

About SemIsrael Virtual Technology Week 2020

Registration is available at this link.

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Hideki Sugimoto, CTO

    NSITEXE, a group company of DENSO Corporation

    For the automotive market our customers expect the highest standards of quality and design assurance. NSITEXE selected the Imperas Vector Extensions Compliance test cases and RISC-V Reference Model as a foundation for our simulation-based design verification (DV) plans.

  • Karel Masarik, CEO and Co-Founder

    Codasip Ltd

    As RISC-V adoption grows throughout the industry in a variety of application areas, so does the need for robust simulation support from both commercial and open source suppliers. We welcome Imperas' contributions to the rapidly accelerating RISC-V ecosystem.