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Imperas at the RISC-V Forum on Vectors and Machine Learning, September 15 2021

Imperas participating at the online virtual event highlighting hardware Design Verification of RISC-V Vector Extensions and software development for Machine Learning applications.

RISC-V Forum on Vectors and Machine Learning

Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced their participation at the RISC-V Forum on Vectors and Machine Learning, September 15th 2021. An online virtual event covering the latest trends and developments with RISC-V Vector Extensions for Machine Leaning applications. To support hardware implementations Imperas will present the latest advances in verification of RISC-V processors and Vector Extensions, and for software developers the use of virtual platforms to shift-left the key project schedules. 


Software Development for ML and RISC-V Vector Accelerators
•    Co-author:    Simon Davidmann – Imperas Software
•    Co-author:    Lee Moore – Imperas Software
•    When:           September 15th 2021 at 8:35am PDT
The RISC-V Vector Extensions offer developers a wide range of options and configurations to provide hardware acceleration for the key algorithms for compute intensive applications such as Machine Learning. In addition, the RISC-V ISA (Instruction Set Architecture) supports custom instructions and heterogeneous multicore arrays that can scale to address the most demanding requirements. 
This talk will highlight the eSol project that successfully mixed an Arm Corex-A57 and 16 RISC V cores to accelerate the ALEXNET image recognition deep neural network as a custom hardware accelerator. Using standard training datasets, the workload requirements across the processor array was established for the key metrics for performance and optimization. Further software development helped to fine tune the application and provide test cases that can be used throughout the hardware design and verification process. While the investment in custom hardware accelerators is significant, the support for future software developers is essential for adoption. This early phase software-based analysis helps to jump-start the software optimization, lifecycle management, and the increasing importance of digital twins as operational references.   


Design Verification with Step-and-Compare for RISC-V Vector Extensions
•    Co-author:    Lee Moore – Imperas Software
•    Co-author:    Simon Davidmann – Imperas Software
•    When:           September 15th 2021 at 9:15am PDT
The RISC-V vector extensions represent the most extensive and complex extensions yet for the RISC-V ISA. As a flexible and modular ISA (Instruction Set Architecture) the RISC-V standard extensions offer developers significant flexibility to configure and tune an implementation to the target application needs and requirements. The RISC-V Vectors Extensions offer extensive options and configurations to address a wide range of hardware accelerator requirements. Thus, designs span from edge devices to cloud based accelerators, across the spectrum of compute requirements.
The verification complexity of the Vector accelerator engine is supported with the adaption of the step-and-compare verification methodology to address the coverage and score-boarding requirements for the RISC-V Vector Extensions. Using a specification envelope model allows the testbench to cover the full range of the options including asynchronous and debug events, plus testing the regular scalar base core. As a general flow the test-bench also supports custom Vector instructions to anticipate future enhancements.


Free! Registration is free for the RISC-V Forum: Vectors and Machine Learning, see more details at this link.


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