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Imperas at 3rd edacentrum Workshop on RISC-V Activities, October 8th 2020

Imperas will present a talk on using RISC-V reference models for processor design verification, software development and SoC Architectural Exploration.

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Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation at 3rd edacentrum Workshop on RISC-V Activities. An online virtual event featuring presentations on the latest developments from across the spectrum of RISC-V activities from academic research, commercial and ecosystem contributors.


‘RISC-V Models for Verification, Software Development and Architectural Exploration’

  • Speaker:         Larry Lapides – Imperas Software
  • When:             12:55 - 13:40 Session 4 Virtual Prototype (VP)

Abstract: As RISC-V processors start to be used more and more in SoCs, industry needs to look beyond the RISC-V ISA to the requirements for use. These include a well-verified implementation, the ability to develop, debug and test software, especially early in the project, and the need to explore different implementations, including different processors, multi-hart processors and custom instructions. One common element to these requirements is a high quality model of the RISC-V cores being used. This presentation will report on the test driven development methodology used to build the Open Virtual Platforms (OVP) models of RISC-V cores (~50 different cores available in the OVP Library and provided to processor IP developers), and show how these models have been used for design verification, software development and architectural exploration.


About the 3rd edacentrum Workshop on RISC-V Activities
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About Imperas

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