A fundamental shift in the economics of processing and new use cases are making ASICs cool again.
Semiconductor Engineering sat down to discuss bespoke silicon and what’s driving that customization with Kam Kittrell, vice president of product management in the Digital & Signoff group at Cadence; Rupert Baines, chief marketing officer at Codasip; Kevin McDermott, vice president of marketing at Imperas; Mo Faisal, CEO of Movellus; Ankur Gupta, vice president and general manager of Siemens EDA’s Tessent Division; and Marc Swinnen, director of product marketing at Ansys.
SE: The term ‘bespoke silicon’ is becoming more popular. Is there an agreed-upon definition?
McDermott: The idea of bespoke silicon started off with ASICs. When my career started, we were designing custom silicon because we just wanted the right thing to do the right job at the right time. And we wanted it our way, so doing an ASIC was a natural choice. At that time, 100,000 gates was a complex design, the NRE fee was not too bad, and volume was modest.
As the process costs changed, ASICs seemed to fall out of favor. If you’d asked this same question five years ago, no one was doing custom designs. Then along came RISC-V. You can adapt processing, you can do things your way. It’s just the right fit. At the same time, Moore’s Law seems to be tapering off, which means processes don’t give you the advantage they once did. It costs a lot more and you get less for the buck. People are starting to realize that one-size-fits-all approach doesn’t quite work. You’re giving up margin in multiple areas. These designs have hundreds of cores. Why aren’t they all doing just what they want in the right space, at the right time, for the right thing? Doing the right job, power efficiently, area efficiently, on time is a no-brainer. Custom silicon is back and hardware is cool….
To read the full Semiconductor Engineering article by Ann Steffora Mutschler, click here.