Imperas will present an update on the latest developments on RISC-V processor functional verification with examples of open-source and commercial implementations
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at the third 2022 SemIsrael Tech Webinar. An online virtual event featuring presentations on the latest updates for the design and development of semiconductor ICs and SoC’s.
‘Advanced RISC-V processor verification and methodologies’
• Speaker: Larry Lapides – Imperas Software
• When: September 13, 2022 – TBD (Tel Aviv, Israel)
Abstract: The open standard RISC-V Instruction Set Architecture (ISA) is driving a new wave of innovation through the SoC and hardware design teams. With RISC-V it is possible to build an optimized processor with just the right mix of features and functions, using standard extensions and custom instructions that leverage the growing ecosystem of software and tools. RISC-V provides developers new design freedoms and flexibility, but with these innovations the challenge will be to achieve time-to-market with a fully verified, production ready RISC-V implementation.
This talk will outline the latest advances in RISC-V functional verification to address the demands of high-reliability and automotive applications, including the innovations in processor designs with features such as: out-of-order pipelines, hardware multi-threading, multi-hart, custom extensions and advanced privileged modes, plus vector accelerators.
Key updates will focus on functional coverage, Verification IP (VIP) and testbenches for asynchronous events, with examples from customers, partners and users at the forefront of RISC-V adoption.
About the SemIsrael Tech Webinar
For more information see this link.
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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