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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Imperas Paper at DVCon 2014 Santa Clara Learning From Advanced Hardware Verification for Hardware Dependent Software

Abstract:
We present a new perspective for embedded software verification for generalized multicore processor platforms,
somewhat analogous to simulation-centric hardware verification solutions. A spatial, temporal, and abstract
multi-dimensional framework for software verification, profiling, analysis, and debug is proposed that leverages a
specialized simulation core. The simulator enables key services for the verification solution while providing a degree of
separation from both the hardware models and software under test, to ensure accurate behavioral representation, as well as
customization and performance advantages.

This paper discusses requirements for modern embedded software development and
solutions utilized to date, before discussing this simulation-based solution and the dimensional framework layered above.
We will also discuss two real life scenarios where the solution is utilized to affect.

View Document

Comments

  • Shubhodeep Roy Choudhury, Managing Director & Co-founder

    Valtrix Systems

    As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve.

    Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification

  • Sandeep Vij, President and CEO

    MIPS Technologies

    We chose Imperas and the Open Virtual Platform technology because of the quality of the models and technology.  We see the positive momentum and leadership position of OVP, and believe this is the best technology for instruction accurate simulation of processor core models.