Imperas on OpenHW TV – Verification of CORE-V open source RISC-V processor IP cores using Imperas RISC-V reference model. Recording now available!
Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation in the first episode of OpenHW TV focused on the Verification of CORE-V open source RISC-V processor IP cores. Guests include the new Co-Chairs of the OpenHW verification task group (Futurewei and SiliconLabs) with contributing members Imperas and Metrics highlighting the open source CORE-V processor IP Design Verification (DV) plan using state of the art flows and SystemVerilog UVM testbenches with encapsulated Imperas RISC-V reference model, coverage based flow, and Metrics flexible cloud based environment.
Following the updates and presentations by Imperas and Metrics all the panellist will be available for the live Q&A session with audience participation.
Please email firstname.lastname@example.org to request a demo or suggest questions for the Q&A session.
- What: OpenHW TV – Episode #1 on Processor Verification
- Where: Virtual online event
- When: June 18, 2020
- Time Zones: 4pm in London and 8am in San Jose, CA
The recording is now available at this link.
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