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Extending SoC Design Verification Methods for RISC-V Processor DV

The July 2020 edition of Mentor Graphics', a Siemens Business, Verification Horizons article and Verification Academy presentation on RISC-V Processor DV are now available online

Verification Horizons


As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established SoC verifications tasks and methods are well proven, yet depend on the industry wide assumption of ‘known good processor IP’ based on the quality expectations associated with IP providers such as Arm or MIPS Technologies. However, the new DV challenges are not purely focused on the processor IP, since an Open ISA allows much greater design freedom whose impact extends well into the SoC itself …


The full Verification Horizons article and recording of the Verification Academy presentation are available online, click here.