Embedded World 2023 Conference Presentation:
RISC-V is not a processor, it is an open specification that offers the flexibility to build optimized processors. This flexibility, however, is a break from the established norms of processor ecosystems that develop around popular processor hardware and development boards. Traditionally the ecosystem followed after the hardware, and flexibility was not included. The innovation of RISC-V is to reverse this approach and lead with the ecosystem enabled for the envelope of possibilities for RISC-V.
This talk focuses on the main aspects required for adoption of RISC-V: tools and methodology for processor verification and software development. Processor verification flows need to support the flexibility of RISC-V while providing comprehensive DV for dependable quality. Ease of use through standard interfaces and verification IP are critical to successful processor DV. For software, the traditional software development tools followed from the top-down selection process of hardware first and then tools for that fixed target configuration. The new RISC-V software development tools start with the application requirements first and allow developers to explore all potential options now available with RISC-V: custom processor cores, commercial IP providers, open-source projects, and extensions with custom instructions.
The new ecosystem is crossing the traditional boundary of commercial providers, open-source projects, and industry collaborations to support the growing RISC-V community.
Speaker: Larry Lapides – Imperas Software
Co-authors: Mike Thompson – OpenHW Group
Davide Schiavone – OpenHW Group
Kevin McDermott – Imperas Software
Simon Davidmann – Imperas Software