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DVCon2022 Tutorial on the 5 levels of RISC-V Processor Verification


The RISC-V open standard ISA (Instruction Set Architecture) offers developers the opportunity to configure the features and functions of a custom processor to uniquely address their target end application needs and requirements. RISC-V has a modular structure with many standard instruction extensions for additional dedicated hardware features such as Floating Point, Bit Manipulation, DSP, Cryptographic, Vectors, and many others currently under development. In addition, custom instructions can be added to further optimize the design. This tutorial covers some of the options and latest trends in simulation-based RISC-V processor verification based on industry standards with UVM and SystemVerilog test benches. With an in-depth review of the new open standard RVVI (RISC-V Verification Interface), this tutorial will include examples of RISC-V test benches with leading EDA tools and SoC DV flows adapted for the complexities of RISC-V processor verification. Starting with entry level, and basic trace compare followed by a detailed review of the latest approaches with Data-path lockstep-compare and Asynchronous lockstep-compare. Examples will be shown based on some popular open-source cores, including a comparison of the different DV methods and options.

Speaker:       Simon Davidmann – Imperas Software
Speaker:       Lee Moore – Imperas Software

The video of this presentation is available at this link on YouTube.