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DVCon 2023 Workshop: Understanding the RISC-V Verification Ecosystem

DVCon 2023 Workshop:

As RISC-V processor technology continues to gain traction the practice of RISC-V processor functional verification is advancing and evolving. What started as a nebulous task with knowledge and proprietary best practices confined within a few commercial organizations is now changing. Today there are various methodologies and tools publicly available that can be selected based on the verification quality objectives of the project. Tools and techniques have evolved so that it’s no longer necessary to build it all yourself or reinvent the wheel. There are resources to help get started, from open-source examples to commercial offerings such as RISC-V processor verification IP. 

This workshop will help the audience understand and navigate the RISC-V verification ecosystem. Some of the topics covered include:

  • Understanding the tools used in RISC-V processor verification: instruction set simulators, processor reference models, random instruction stream generators, verification IP
  • Compare and contrast techniques that can be used for RISC-V processor verification: post-simulation trace compare, self-checking tests, lockstep co-simulation, functional coverage
  • Open standards for RISC-V processor verification: RISC-V Verification Interface (RVVI)
  • Open-source examples and commercial offerings

At the conclusion the audience will leave the information needed to make a decision about the best solution for their RISC-V processor verification project.  

Presenters:    Aimee Sutton – Imperas Software
                          Simon Davidmann – Imperas Software