CDNLive is March 11-12 in Santa Clara, California and is organized by Cadence Design Systems.  Imperas will be presenting a paper titled “Software Quality is Directly Proportional to Simulation Speed” as part of Track 6, at 4pm Tuesday March 11th.  Here is the abstract: 

“Software quality is directly proportional to simulation speed.”  This is obvious, even intuitive, for engineers.  Faster simulations mean more tests can be run, which in turn means more bugs can be found, which results in higher quality.  Reduced schedules can be a side benefit of speed. 

While this is obvious, why is it so important right now?  One example is server SoCs, where software/systems test suites can include hundreds of…

DVCon is March 3-6 in San Jose, California.  Imperas will be presenting a paper titled “Learning From Advanced Hardware Verification for Hardware Dependent Software” as part of Session 3, at 9:30am Tuesday March 4th.  Here is the abstract: 

We present a new perspective for embedded software verification for generalized multicore processor platforms, somewhat analogous to simulation-centric hardware verification solutions. A spatial, temporal, and abstract multi-dimensional framework for software verification, profiling, analysis, and debug is proposed that leverages a specialized simulation core. The simulator enables key services for the verification solution while providing a degree of separation from both the hardware models and software under…

Embedded World is February 25-27 in Nuremberg, Germany.  Imperas will be presenting a paper titled “Customized, Intelligent Memory Access Monitoring for Reliable Asymmetric MultiProcessor System Development” in Session 23, Thursday at 14:00.  We will be available for demos of the Imperas simulation and software development, debug and test tools in the Altera booth Tuesday and Wednesday from 10:00-11:00 and 14:00-15:00, and Thursday from 10:00-11:00.  We will also be in the Imagination Technologies booth for demos of the Imperas tools for MIPS cores.

Here is a brief summary of the paper: 

The use of Asymmetric MultiProcessor (AMP) architectures is now widespread.  Two common implementations are Linux running on one core…

Embedded Technology 2013 ( http://www.embeddedtech.net/), November 20-22 in Yokohama, Japan, is the world’s largest  trade show and conference for embedded system designers and  managers.  The ET Conference & Exhibition introduces advanced technologies and solutions for emerging embedded applications, including digital consumer electronics,  automotive, wireless/ubiquitous computing and factory automation.

Imperas will again this year have a booth in the Venture Village area of the exhibit hall.  Imperas will demonstrate both OVP and Imperas tools, showing how virtual platform based technologies can provide benefits such as earlier software development (pre-silicon),…

ARM Techcon 2013 ( http://www.armtechcon.com/), October 29-31 in Santa Clara, California, is the largest conference devoted to developers of ARM-based SoCs, software and systems, bringing together users, hardware and software vendors, ARM technologists and others in the ARM ecosystem.

Imperas at ARM Techcon:  Simon Davidmann will be participating on a panel session, and Imperas will have a booth in the exhibits. 

Panel title:  The Future of Collaborative Embedded SW Development, from the viewpoint of one Technology Chain Gang

Panel abstract:  The creation of a modern embedded processor platform solution requires components from a “technology chain” of…

The Microelectronics Support Centre at STFC Rutherford Appleton Laboratory is holding a free Virtual Prototyping information day with hands-on lab sessions, featuring Cadence VSP, Imperas, and the Xilinx Zynq™ Virtual Platform.  Imperas was recently added to the Europractice vendor list. 

The information day will include technical presentations from Imperas on OVP fast processor models and the Imperas M*SIM simulator, and Cadence on the Virtual System Platform (VSP) tool.  The Cadence virtual platform of the Xilinx Zynq device uses the Imperas OVP model of the dual core ARM Cortex™-A9 with the M*SIM simulator. 
A hands-on Imperas lab will allow attendees to explore the Imperas tools, by building a system using an OVP…

If you are heading to the Design Automation Conference (DAC) in Austin, Texas, taking place June 2-6, Larry Lapides will be attending.  He would enjoy learning more about your virtual platform and software development requirements, as well as discussing the second generation Imperas products, including the Developer range of products and M*SDK.  Please contact sales@imperas.com to set up a meeting at DAC.

The Multicore Developers Conference (MDC) is focused on the discussion of both technical and business issues of designing and using multicore processors.   

Imperas at MDC:  Larry Lapides is presenting a paper, and Imperas will have a booth in the exhibits where we will be demonstrating solutions for software verification, analysis and profiling, ranging from code coverage and profiling to OS context switching analysis and fault injection.  Exhibit hours are Tuesday 12:30 – 2:30pm and 4:30 – 6:30pm, and Wednesday 12:15 – 2:15pm. 

Virtual Platform Based Software Debug & Testing for Multiprocessor/Multicore Systems, Larry Lapides, Wednesday May 22, 3:45pm

Abstract: 
As…