The Microelectronics Support Centre at STFC Rutherford Appleton Laboratory is holding a free Virtual Prototyping information day with hands-on lab sessions, featuring Cadence VSP, Imperas, and the Xilinx Zynq™ Virtual Platform. Imperas was recently added to the Europractice vendor list.
The information day will include technical presentations from Imperas on OVP fast processor models and the Imperas M*SIM simulator, and Cadence on the Virtual System Platform (VSP) tool. The Cadence virtual platform of the Xilinx Zynq device uses the Imperas OVP model of the dual core ARM Cortex™-A9 with the M*SIM simulator.
A hands-on Imperas lab will allow attendees to explore the Imperas tools, by building a system using an OVP…
If you are heading to the Design Automation Conference (DAC) in Austin, Texas, taking place June 2-6, Larry Lapides will be attending. He would enjoy learning more about your virtual platform and software development requirements, as well as discussing the second generation Imperas products, including the Developer range of products and M*SDK. Please contact firstname.lastname@example.org to set up a meeting at DAC.
The Multicore Developers Conference (MDC) is focused on the discussion of both technical and business issues of designing and using multicore processors.
Imperas at MDC: Larry Lapides is presenting a paper, and Imperas will have a booth in the exhibits where we will be demonstrating solutions for software verification, analysis and profiling, ranging from code coverage and profiling to OS context switching analysis and fault injection. Exhibit hours are Tuesday 12:30 – 2:30pm and 4:30 – 6:30pm, and Wednesday 12:15 – 2:15pm.
Virtual Platform Based Software Debug & Testing for Multiprocessor/Multicore Systems, Larry Lapides, Wednesday May 22, 3:45pm