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The Verification Mindset

What makes a good verification engineer? It’s not always about technical expertise, and it’s rarely just about verification.

Semiconductor Engineering

 

The practice of semiconductor verification has changed substantially over the years, and will continue to do so. The skillset needed for functional verification 20 years ago is hardly recognizable as a verification skillset today, and the same should be expected moving forward as design and verification becomes more abstract, the boundary of what is implemented in hardware versus firmware and software continues to move, as well as the adoption of new technologies. A move toward a complete verification spectrum is a constant response to the constant increase in complexity and time-to-market pressures.
This means the definition of a good verification engineer changes over time….
 

To read the full Semiconductor Engineering article by Ann Steffora Mutschler, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

ARM TrustZone Platform Modeling Application Note

Comments

  •  Steve Richmond, Co-chair of the OpenHW Group Verification Task Group

    Silicon Laboratories

    Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog.

    The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.

  • Allen Baum, Chair of the RISC-V International Architecture Test SIG

    Esperanto Technologies, Inc.

    Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture.

    The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.