Embedded World is February 25-27 in Nuremberg, Germany. Imperas will be presenting a paper titled “Customized, Intelligent Memory Access Monitoring for Reliable Asymmetric MultiProcessor System Development” in Session 23, Thursday at 14:00. We will be available for demos of the Imperas simulation and software development, debug and test tools in the Altera booth Tuesday and Wednesday from 10:00-11:00 and 14:00-15:00, and Thursday from 10:00-11:00. We will also be in the Imagination Technologies booth for demos of the Imperas tools for MIPS cores.
Here is a brief summary of the paper:
The use of Asymmetric MultiProcessor (AMP) architectures is now widespread. Two common implementations are Linux running on one core of a dual-core ARM Cortex-A9, with an RTOS running on the other, and SMP Linux running on the dual-core ARM Cortex-A9 and an RTOS or bare metal application running on another processor core, such as an Altera NIOS II. The reliability of such a system is highly dependent on the correct functioning of inter-core interaction with shared resources, which is often hard to verify.
This paper will detail the methodology used to bring up such an AMP system on a virtual platform. The first step is the construction of the instruction accurate virtual platform for the two AMP systems. The Open Virtual Platforms APIs for model and platform development are used in building the virtual platforms used in this paper. These virtual platforms are variants of the Altera SoC FPGA Cyclone V product. The second step in the process involves the use of CPU- and OS-aware analysis tools to help with initial system bring up. Rather than providing only instruction trace data, these tools enable the analysis of the system at the appropriate level of abstraction for the software engineer: C source code for firmware and drivers and the OS task/event level for operating systems. In addition, the tools are non-intrusive, requiring no instrumentation or modification of the application or OS, thus validating the results of the analysis.
Finally, the third step is the development of a robust test environment, including the use of non-intrusive, intelligent memory access monitors, built upon the CPU- and OS- aware simulation environment to ensure that different OS operations do not access forbidden memory segments.
A detailed case study illustrating how complex faults have been found in an Altera Cyclone V AMP system, by using this methodology, will be shown.