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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

SemiEng: A Minimal RISC-V

Is there room for an even smaller version of a RISC-V processor that could replace 8-bit microcontrollers?

Semiconductor Engineering

 

Microcontrollers exist in almost everything, but can RISC-V satisfy the needs of this market? Is it small enough to replace 8-bit processors? What might help people migrate to a more modern processor architecture?
RISC-V defines a 32-bit processor instruction set architecture (ISA) that is open…

 

To read the full Semiconductor Engineering article by Brian Bailey, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Custom Instruction Flow Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Comments

  • Jean-Michel Fernandez, ESL Product Line Director

    Magillem

    The wide support of OVP fast processor core models, together with Imperas tools for software analysis, perfectly complements the Magillem Executable Specification (X-Spec) solution. The tight integration of Imperas technology with Magillem X-Spec will help our customers to seamlessly execute their embedded Software on their Hardware specification.

  • Philippe Berger, CEO

    Dolphin Design

    Our verification methodology for the Panther DSP/AI Accelerator IP needs to address not just the full range of the current configuration options but also the roadmap for Panther. 

    ImperasDV is the cornerstone of our simulation-based DV strategy, with the Imperas golden reference model, scoreboard, verification IP, functional coverage analysis and debug efficiency.