Imperas will present the latest updates for RISC-V developers including RISC-V processor design verification and pre-silicon software development
Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced their participation at the 2023 SemIsrael Tech Webinar. An online virtual event featuring presentations on the latest updates for the design and development of semiconductor ICs and SoC’s.
RISC-V Models for Verification, Architectural Exploration, and Software Development
• Speaker: Larry Lapides – Imperas Software
• When: February 14, 2023 – 4:30pm (Israel Time Zone)
Abstract: The design freedoms of RISC-V offer systems and SoC developers new flexibility to optimize a processor for the requirements of the target application. Now Architectural Exploration is not just about the configuration of multi-core designs, but the analysis of the application and potential advantages of custom instructions. Custom extension can boost the performance for a target class of operations, or support new multi-core communication methods. Software development with virtual prototypes is well established, but new to RISC-V is the advantage of these platforms offer to end users migrating legacy applications to the new RISC-V based device, well before silicon is available. For SoC teams optimizing a RISC-V processor they also need to address the additional challenge of RISC-V verification, open standards such as RVVI (RISC-V Verification Interface) are helping the ecosystem support for standards-based test benches and Verification IP. This talk highlights the RISC-V models that are unifying the hardware, software, and verification teams across all phases of RISC-V projects with dependable quality and efficiency.
About the SemIsrael Tech Webinar
For more information and free registration see this link.
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