Imperas will present the latest updates on verification methodologies for RISC-V processor developers exploring the potential of the open standard ISA.
Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced their participation at the 2023 SemIsrael Tech Webinar. An online virtual event featuring presentations on the latest updates for the design and development of semiconductor ICs and SoC’s.
Advanced RISC-V Processor Verification Methodology
Abstract: The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this also implies the SoC design verification teams will need to address the challenge and complexity of processor verification.
This presentation outlines methodologies that assist in both the efficiency and support for the growing community of RISC-V adopters. The focus is on more complex RISC-V processors, and methodologies that account for asynchronous events: interrupts and debug operations, plus hardware configurations including multi-issue and Out-Of-Order pipelines, multi-hart processors, vector extensions and custom instructions.
• Speaker: Larry Lapides – Imperas Software
• When: Tuesday May 2, 2023 – 4:30pm (Israel Daylight Time)
About the SemIsrael Tech Webinar
For more information and free registration please visit this link.
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