Imperas, UltraSoC and Codasip Present a Tutorial on Design and Verification of Designs Based on RISC-V
Imperas will co-present a tutorial at the 2018 Design and Verification Conference & Exhibition Europe (DVCon Europe), including discussion of virtual platforms and software development environments for designs based on RISC-V. We hope to see you there!
Please email email@example.com to meet with Imperas on virtual platforms for embedded software and systems development, debug and test, at DVCon Europe!
Tutorial: “RISC-V Design and Verification.”
· Organized by Kevin McDermottof Imperas Software.
- Zdenek Prikryl- Codasip Ltd.
- Kevin McDermott– Imperas Software Ltd.
- Peter Shields- UltraSoC Technologies Ltd.
· When: October 24, 11:45am - 1:15pm | Tutorial 7
About DVCon Europe 2018
DVCon Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. It brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.
· Where: Holiday Inn, Munich City Centre in Munich, Germany.
· When: October 24-25, 2018.
· See: https://dvcon-europe.org/ and follow on #dvconeurope.
About the RISC-V Foundation
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 100 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation. See https://riscv.org/
UltraSoC is an independent provider of SoC infrastructure that enables rapid development of embedded systems based on advanced SoC devices. The company is headquartered in Cambridge, United Kingdom. Visit www.ultrasoc.com
Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. Visit www.codasip.com.