Skip to main content

Webinar: Optimizing embedded RISC-V HW / SW development from virtual models to in-life silicon instrumentation, July 15 2020

Imperas with Andes and UltraSoC are co-hosting a webinar series on the latest challenges’ designers are facing migrating AI/ML applications to custom SoCs with RISC-V - Recording now available on-line!

RISC-V Webinar with Andes, Imperas and UltraSoC

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced together with Andes and UltraSoC the latest webinar for SoC designers developing next generation devices on the use of virtual platforms and FPGA’s for RISC-V multicore SoCs prototypes, covering early SW development, HW verification and analysis for system level design optimization.

Webinar: “Optimizing embedded RISC-V Hardware / Software development from virtual models to in-life silicon instrumentation”

Outline: This webinar will cover the key hardware and software prototyping phase, including demos with example platforms to test multicore processing elements, which are the foundational building blocks of AI Inferencing or ML designs.

The Agenda will cover the key prototype phases of RISC-V based SoC design:
•    Imperas: Virtual platforms as early evaluation & demo ‘boards’ - Early software development including debug and verification
•    Andes: Processor cores implemented as FPGA prototypes - Optimized features for Cores and Processor sub-systems
•    UltraSoC: Advanced analytics with FPGA prototypes - Debug & Trace, and On-Chip performance monitors and analytics

The webinar will conclude with a live hosted Q&A session with all the presenters as a group discussion.

Wednesday July 15th 2020
With two meeting time slots available to choose from: Starting at 8am (PDT) or 5pm (PDT)

Recording now available at this link.

About Imperas

For more information about Imperas, please see Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

# # #