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Imperas and Andes co-host RISC-V Seattle virtual Meetup, April 2 2020

Imperas and Andes are guest hosts for the next Seattle RISC-V virtual Meetup

RISC-V Seattle Meetup April 2020

 

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced the next Seattle Area RISC-V Meetup as a virtual event to be co-hosted with Andes Technology.

Andes presentation will provide the latest updates on RISC-V P-ext, V-ext and custom instructions for AI and Machine Learning.
Imperas presentation will cover virtual platforms for architecture analysis, software development and RISC-V reference models for processor design verification (DV).


Speakers:    Larry Lapides, Imperas Software and Charlie Cheng, Andes Technology


When:          Thursday April 2, 7:00pm – 8:30pm
Where:         Online virtual meetup

Recording and PDFs of the slides are now available at this link.

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Custom Instruction Flow Application Note

RISC-V Custom Instruction Flow Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Mike Ingster, President and Founder

    Quantum Leap Sales

    Imperas solutions for early software development have never been more appropriate with development schedules more critical than ever. We believe that simulation-based verification is fast becoming an essential requirement in complex SoCs, and together with advanced debug and analysis tools for many-core and heterogeneous designs will greatly reduce development schedules for next generation devices.

  • Alexander Redkin, CEO

    Syntacore

    As one of the first IP providers for RISC-V cores, we see the importance of compliance as the RISC-V ecosystem develops. riscvOVPsim is a solid starting point for developers looking for a RISC V ISS (Instruction Set Simulator) for test and verification.