In November 2016, Simon Davidmann of Imperas gave a talk on how Imperas technology is being used for Timing Analysis, Power Analysis and Fault Simulation
to assist with Software Verification. Here are the slides. The talk was split into two sections.
The first section covers software verification for embedded systems and provides an overview of the challenges of many processors
in current embedded systems. It leads into the requirements for software verification and introduces specific embedded software development issues. It then
explains using simulation / virtual platforms and advanced tools to make embedded software development easier, quicker, and more affordable.
There are explanations of how simulation can be used with continuous integration and other modern software development practices.
The second section of the talk introduces the issues related to low power and how to use simulation to get a handle on the affects of software on low power design.
Imperas is collaborating with several institutes and universities around the world and these collaborations are explored.
The use of Imperas Instruction Accurate simulation used for Timing Analysis, Power Analysis and Fault Simulation are discussed with examples and case studies.