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Imperas at DAC: Design Automation Conference, December 5-9 2021

Imperas will be participating on the RISC-V Pavilion within the DAC exhibit area for in-person demonstrations and discussions with the Imperas team, presentations will also be featured in both the DAC and RISC-V Summit technical conferences which are co-located for 2021.


DAC - Design Automation Conference 2021

Imperas Software Ltd., the leader in simulation solutions for RISC-V, today announced their participation at DAC 2021 on the RISC-V pavilion with presentations and exhibition booth for demos and discussions. For 2021 the RISC-V Summit will be co-located with DAC, see more details on the complete Imperas activities during the RISC-V Summit at this link

Imperas activities at DAC 2021

RISC-V processor verification methodology with dynamic testbench for asynchronous events
     •    Speaker:    Man Wai (Manny) Wright – Imperas Software
     •    When:        Monday, December 6th, 5:00pm - 6:00pm
     •    Where:       Designer, IP and Embedded Systems Poster Networking Reception
Abstract: For SoC designers adopting RISC-V, tackling the processor DV tasks presents some new challenges. The established SoC flows have some standard assumptions – test benches written for UVM SystemVerilog flows and known good processor IP from a mainstream supplier. With the availability of open source RISC V cores and the growing interest to modify or add custom extensions is increasing the DV tasks. The basic RISC-V compliance suite is insufficient to achieve the coverage requirements for a complete DV test plan, and comparison-based testing with predicted results has built-in limitations. The latest work on dynamic test benches allows the processor RTL to be subjected to the full range of asynchronous events and debug operations. Interactive dynamic test benches allow both detection of issues and also efficient investigation for a timely resolution. This paper will present the latest results from extensively testing some popular open source cores with an open test bench.


SoC Architectural Exploration for AI and ML accelerators with RISC-V
     •    Speaker:    Katherine (Kat) Hsu  – Imperas Software
     •    When:        Monday, December 6th, 11:10am - 11:30am
     •    Where:       Designer, IP and Embedded Systems Track
Abstract: SoC developers and system designers are looking at hardware acceleration options for AI and Machine Learning applications moving from cloud-based algorithms to dedicated hardware. Since the algorithms are already configured for multicore support the tradeoffs become focused on the structure of processor arrays and the optimum performance requirements at each node. In addition to the flexibility offered by the open standard ISA of RISC-V to configure the core features to match the compute requirement, RISC-V offers the options to add custom extensions and instructions that allows a greater degree of system optimization. New extensions can be targeted at the application workload or as dedicated communication channels between the cores, nodes and/or interfaces to the NoC. This talk covers a methodology to evaluate the hardware options by enabling early system architectural exploration using software to uncover the optimum design configurations.

Exhibit: Stop by the Imperas booth on the RISC-V Pavilion and see all the latest demonstrations of Imperas simulation technology and virtual platforms for RISC-V software development, and RISC-V processor verification. The Imperas RISC-V golden reference model supports all the latest RISC-V specifications including Vectors. For more information, or to schedule a demonstration session at DAC 2021, please contact the Imperas team via

About Virtual DAC 2021
For more information see

About Imperas

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