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DVCon 2022: Introduction to RISC-V CPU design verification


With all the design flexibility and innovations supported by the open standard ISA of RISC-V, quality processor verification is now another flexible option.
This talk gives an introduction and overview of the Imperas presentations and announcements at DVCon 2022.

Speaker:       Kevin McDermott – Imperas Software

The video of this presentation is available at this link on YouTube.