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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Altera Nios II Processor Model Delivered By Imperas

Open source simulation model enables Altera customers to more easily validate and debug Nios II embedded software

San Jose, Calif., October 22nd, 2013—Imperas Software Ltd. (www.imperas.com), founder of the Open Virtual Platforms™ (OVP™) consortium, today announced the availability of the Altera Nios II embedded processor OVP model. Jointly developed by Imperas and Altera, this open source model will enable a high-performance development environment for Nios II embedded software.

The OVP Fast Processor Model of the Nios II may be configured at start-up to match the intended behavior of the actual FPGA component, but will execute significantly faster than real-time. This allows embedded software to be tested more rigorously and earlier in the design process, accelerating complex software development cycles.

“Imperas led formation of the Open Virtual Platforms consortium to improve the embedded software development experience,” said Simon Davidmann, CEO of Imperas. “With Altera, we have taken an important step today by providing designers with a high-performance model of the Altera Nios II processor, executing many times faster than other development offerings to enable the most comprehensive software verification solution available.”

The model and underlying simulator includes a comprehensive application program interface (API) that extends visibility into the processor behavior. This allows the designer to run embedded software, either from Altera or their own code, and leverage advanced analysis and debug operations, including operating system awareness.

“Engineers are seeking rapid development methods that also provide immediate feedback on configuration or customization, said Premal Buch, vice president, Software Engineering, Altera. “The Altera Nios II device has been the most widely used FPGA-based processor for many years, and this OVP model will help customers expand their design options.”

The complexity of system modeling in multi-core and multi-processor environments is driving the need for advanced virtual platform development and verification environments. Verification technologies that operate at a range of abstractions, including CPU- and OS-Aware levels, and that can provide customizable operations that work intimately with the design, are required. The performance of these systems will become more critical as the volume of tests required increase.

The new model of Altera’s Nios II processor will be showcased in the Imperas booth, number 520, at ARM TechCon, October 29–31, 2013.

Availability
The Altera Nios II OVP processor model is available now, and may be downloaded from the OVP website: www.OVPworld.org/Nios_II.

About Imperas and OVP
Imperas Software was founded in 2008 to develop and deliver embedded software development systems. The company’s comprehensive product line enables the rapid creation of high-performance virtual platforms and the efficient development of embedded software utilizing those platforms. Imperas’ technology allows for software engineering schedules to be significantly reduced while improving the quality of products relying on embedded systems. In 2008 Imperas founded the Open Virtual Platforms (OVP) consortium to improve the availability of open model libraries and virtual platform infrastructure. Leading communications, automotive, consumer electronics and embedded processor companies rely on Imperas for the development of their electronic products. The company’s corporate headquarters is located near Oxford, UK and it maintains support and sales organizations in Silicon Valley, California and Tokyo, Japan. For more information about Imperas, please go to www.imperas.com.

Imperas, Open Virtual Platforms, OVP, OVPsim, M*SDK, C*DEV, S*DEV, M*DEV, ToolMorphing and SlipStreamer are trademarks of Imperas Software Limited. Altera, Hardcopy and Nios words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries.  Imperas acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Custom Instruction Flow Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Premal Buch, VP Software

    Altera

    Given the wide variety of customer applications for our SoC FPGAs, our software stacks require rigorous and comprehensive testing.  Imperas' M*SDK has proven to be an outstanding environment for the validation and analysis of operating systems, drivers and firmware. Verification using the Imperas solution not only accelerates software bug discovery, but also provides a rapid understanding of the root cause of problems.

  • Professor Jong Tae Kim

    Sungkyunkwan University, Seoul, South Korea - SKKU

    Imperas OVP modeling and high-level simulation platforms unify both hardware and software development for multi-core designs, and are clearly the wave of the future. Access to the University Program allows my students access to advanced technologies essential to their future endeavors.