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An Insider’s View Of Verifying Custom RISC-V Processor Cores

How RISC-V verification ecosystems support flexibility in approaching a custom processor design.

Semiconductor Engineering

 

This article is derived from a talk at the RISC-V Summit in December 2020 that Bill McSpadden, principal verification engineer at Seagate Technology, gave on the challenges and experiences his team faced in the verification of two custom RISC-V processor cores. While a technical presentation at a technical conference may not be completely unexpected, the unique part was the frank acknowledgment that without any hype or fanfare the team tackled some of the most challenging verification problems in the industry today—how an experienced SoC team can verify a custom RISC-V processor…

 

To read the full blog post by Shubhodeep Roy Choudhury (Valtrix Systems) and Lee Moore (Imperas Software) with supporting images courtesy of Bill McSpadden (Seagate Technology) on Semiconductor Engineering, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

ARM TrustZone Platform Modeling Application Note

ARM TrustZone Platform Modeling Application Note

Comments

  • Mark Himelstein, CTO

    RISC-V International

    RISC-V International’s mission is to support the adoption of RISC-V through industry-wide partnerships and collaboration.

    The continued contributions, including the Imperas Open Source Architecture tests, are helping to ensure an ecosystem of compatibility that all members and users can build on.

  • Dr. Luca Benini, chair of digital circuits and systems and one of the originators of the RISC-V PULP project

    ETH Zurich

    RISC-V has made the successful transition from an academic project to achieve commercial adoption. We see a universal need for quality and design assurance that can be supported by riscvOVPsim across all projects as PULP RI5CY cores are increasingly implemented in commercial SoC development.