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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

RISC-V Summit 2022: The New Verification Ecosystem that Supports RISC-V Verification for all Adopters

RISC-V Summit 2022 Conference talk

The RISC-V design freedoms have enabled implementers to innovate new and creative solutions. As a design progresses from concept to completion, the flexibility of RISC-V has implications for the hardware functional verification teams. This talk covers the latest developments in the RISC-V verification ecosystem to address new approaches for processor verification. These include: open standards to support universal testbenches and VIP (Verification IP) reuse, coverage libraries and quantitative measures for test infrastructure quality, and novel techniques to verify cache coherency and SoC integration. Based on examples from several popular open-source cores this talk will provide guidelines that can help both open-source and commercial projects address the RISC-V functional verification challenge.


Speakers:
Lee Moore, Imperas Software Ltd.
John Sotiropoulos, Principal Applications Engineer, Breker Verification Systems
 

The video of this presentation is available on YouTube.

View Document

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

ARM TrustZone Platform Modeling Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Shubhodeep Roy Choudhury, Managing Director & Co-founder

    Valtrix Systems

    Ideally any test should provide a clear pass or fail indication. In the case of RISC-V processor DV this is achieved with a comparison against a quality reference model.

    STING helps generate portable, architecturally correct and self-checking tests targeted at the corner-case scenarios by automating the comparison of the DUT against the Imperas reference model results.

  • Rishiyur Nikhil

    CTO Bluespec Inc. and Chair of RISC-V Formal Task Group

    The RISC-V ISA Formal Spec Task Group will produce a Formal Specification for the RISC-V ISA. We see the introduction of riscvOVPsim as an excellent reference platform to test and verify with.