RISC-V Summit 2022 Conference talk
The RISC-V design freedoms have enabled implementers to innovate new and creative solutions. As a design progresses from concept to completion, the flexibility of RISC-V has implications for the hardware functional verification teams. This talk covers the latest developments in the RISC-V verification ecosystem to address new approaches for processor verification. These include: open standards to support universal testbenches and VIP (Verification IP) reuse, coverage libraries and quantitative measures for test infrastructure quality, and novel techniques to verify cache coherency and SoC integration. Based on examples from several popular open-source cores this talk will provide guidelines that can help both open-source and commercial projects address the RISC-V functional verification challenge.
Lee Moore, Imperas Software Ltd.
John Sotiropoulos, Principal Applications Engineer, Breker Verification Systems
The video of this presentation is available on YouTube.