RISC-V Summit 2022 Expo talk
As an open standard ISA, RISC-V has attracted the attention of system designs, hardware engineers and software developed based on the new freedoms for design optimizations. The OpenHW Group has been formed by members looking to build on the potential of open-source hardware IP as a foundation for further extensions and adoption in mainstream commercial designs. With this surge in design innovation the challenge for the verification task is not just the complexities on modem processor design innovations, but the scale of projects as the DV task moves from a few specialist providers to all adopters that chose to exploit the full potential now available with RISC-V for optimized processors in domain specific applications.
This talk highlights the key aspect of a RISC-V verification plan based on the pioneering work at OpenHW to deliver quality open-source IP cores with industrial strength versification for adoption in the established commercial tools and design flows. With a case study around the CV32E40P as an example for the latest methods of ‘lock-step-compare’ for asynchronous events and debug operations. The new open standard of RVVI (RISC-V Verification Interface) supports the full flexibility of RISC-V for designs with privilege modes, vectors, out-of-order pipelines, multi-threading, multi-heart, plus user defined custom instructions and extensions.
The design side flexibility of RISC-V is driving the innovation in functional verification, RVVI has the flexibility to support the efficiency and verification IP reuse as RISC-V becomes mainstream.
Aimee Sutton, Imperas Software Ltd.
The video of this presentation is available on YouTube.