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RISC-V Summit 2022: Introduction to RISC-V Verification with the Open Standard RVVI (RISC-V Verification Interface)

RISC-V Summit 2022 Expo talk

As an open standard ISA, RISC-V has attracted the attention of system designs, hardware engineers and software developed based on the new freedoms for design optimizations. The OpenHW Group has been formed by members looking to build on the potential of open-source hardware IP as a foundation for further extensions and adoption in mainstream commercial designs. With this surge in design innovation the challenge for the verification task is not just the complexities on modem processor design innovations, but the scale of projects as the DV task moves from a few specialist providers to all adopters that chose to exploit the full potential now available with RISC-V for optimized processors in domain specific applications.

This talk highlights the key aspect of a RISC-V verification plan based on the pioneering work at OpenHW to deliver quality open-source IP cores with industrial strength versification for adoption in the established commercial tools and design flows. With a case study around the CV32E40P as an example for the latest methods of ‘lock-step-compare’ for asynchronous events and debug operations. The new open standard of RVVI (RISC-V Verification Interface) supports the full flexibility of RISC-V for designs with privilege modes, vectors, out-of-order pipelines, multi-threading, multi-heart, plus user defined custom instructions and extensions. 
The design side flexibility of RISC-V is driving the innovation in functional verification, RVVI has the flexibility to support the efficiency and verification IP reuse as RISC-V becomes mainstream.


Presenter:
Aimee Sutton, Imperas Software Ltd.
 

The video of this presentation is available on YouTube.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

RISC-V Custom Instruction Flow Application Note

ARM TrustZone Platform Modeling Application Note

Comments

  • Josh Scheid, Head of Design Verification

    Ventana Micro Systems Inc

    At Ventana, our teams of developers are building the foundational processor IP and chiplet building blocks that will enable a step change in performance for the most demanding compute workload markets.

    Our verification strategy is to exercise the RISC-V based processors across the most demanding scenarios and are using Imperas RISC-V vector test suites in addition to the Imperas golden reference model in our verification environment.

  • Rick O’Connor, President & CEO

    OpenHW Group

    The OpenHW Verification Task Group contributors are pioneers in the drive to advance the quality of open-source hardware IP ready for mainstream adoption – quality deliverables are the hallmark of any trusted IP provider, commercial or open source.

    OpenHW membership growth over the past three years is expanding the roadmap of IP core projects dramatically, with projects addressing the needs for application class devices supporting Linux, embedded security, and compute intensive applications with custom instructions. The RVVI open standard and flexible methodology significantly helps the OpenHW Verification Task Group members and contributors with efficient and quality verification for the full range of CORE-V IP projects.