Imperas and Andes are co-hosting the next RISC-V Austin Group Meeting on optimizing a RISC-V processor with Vector Extensions for AI applications.
Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced the next Austin RISC-V group meeting which will be co-hosted with Andes Technology Corp., a leading supplier of performance-efficient and extensible 32/64-bit RISC-V CPU cores and a Founding Premier member of RISC-V International. The agenda will be focused around exploring and extending RISC-V Vector Accelerators for AI and other applications with talks by Andes, Imperas and guest speaker Dave Baker, VP Digital Design at Luminous Computing who will share Comments on Experiences with RISC-V ISA.
The Real Challenge for RISC-V Vector Processors
John Min, Andes Technology
Solutions to solve the data movement problem including extensive pre-fetching, large dedicated memories and caches come at the cost of power and size. Andes Custom Extension implemented Streaming Port solves the problem with minimal power and gate overhead. ACE can be used for pre- and post-processing data to further boost VPU performance and controlling and managing external accelerators.
Software Development for AI SoCs
Katherine (Kat) Hsu, Imperas Software
An inference SoC for AI/ML – data center or edge – typically has an application processor plus AI accelerator. The AI accelerator will likely be an array of processors and vector engines. This requires optimization of the AI software plus the software managing the workload balancing. This talk will discuss the different tasks of software development for AI SoCs, and how a virtual platform enables the “shift left” of schedules, many months before a FPGA prototype or hardware emulator is available.
When: Tuesday August 17th 2021 at 6:00pm CDT
Where: Virtual Event
Recording now available on YouTube.
For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.
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