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Imperas at the RISC-V World Conference China, June 22-24 2021

Imperas participation will cover RISC-V verification and virtual platforms for early software development before hardware is available.

RISC-V World Conference in China 2021

Imperas Software Ltd., the leader in RISC-V processor verification technology, today announced their participation at the first RISC-V World Conference in China, which will be hosted at Shanghai Tech University from June 22 to 24, 2021. Imperas participation will cover the latest updates for RISC-V verification, including the leading step-and-compare method with the Imperas RISC-V Golden Reference Model. Imperas simulation technology together with software development and analysis tools will be highlighted for use with SoC Architectural Exploration, OS/RTOS porting and software applications.


Imperas activities at the RISC-V World Conference in China 2021: 

RISC-V Reference Models for Verification, Software Development and Architectural Exploration'
•    Speaker:       Katherine (Kat) Hsu – Imperas Software
•    Co-Author:   Lee Moore – Imperas Software
•    When:           TBD
Abstract: The flexibility of the open standard ISA of RISC-V is just the starting point for the next generation of domain specific devices. System designers are exploring new architectural options supported by RISC-V, with configurations across all the standard and custom extensions, using a software driven design approach. Early software development is useful not just to accelerate schedules and time to market but also to provide key insights on the design tradeoffs before the hardware RTL design is finalized. To cover all the custom features and options of RISC-V the standard SoC Design Verification (DV) flow can be adapted to cover the requirements for processor verification using a test bench comparison with a reliable reference model.
This talk will report on the test driven development methodology used to build the Open Virtual Platforms (OVP) open source models of RISC-V cores (covering the specification envelope of RISC-V including the near ratified Crypto (scalar), Bit Manipulation, DSP, and Vector extensions), and show how these models have been used for design verification, software development and architectural exploration. This talk will show examples of industry uses of these models for those use cases, including Step-And-Compare DV flows, software porting and bring up, and optimization of custom instructions.


A Comparison of Different Methodologies for RISC-V Processor Verification
•    Speaker:       Kevin McDermott – Imperas Software
•    When:           TBD
Abstract: The open RISC-V instruction set architecture (ISA) is enabling semiconductor vendors and systems companies to develop their own domain-specific processors, optimized for the target applications needed for a particular market segment. RISC-V based SoCs are being built for applications including IoT, microcontrollers, security, AI/ML and other accelerators, plus other markets. The business and technical flexibility of the open architecture has led a number of companies to implement their own RISC-V processors for their SoCs. With the design of processors comes the requirement for design verification (DV). This can be done with a variety of methodologies, ranging from simple signature-based comparisons for architectural validation to advanced ‘step-and-compare’ flows that support the most complex processors. These most complex processors might have the latest RISC-V specification extensions such as H-Hypervisor and V-Vector, multiple harts and/or other custom features (instructions, registers, interrupt schemes, etc…).

This presentation will review the 5 different DV flows, from signature comparison to trace comparison to step-and-compare, and discuss the tradeoffs in effort, completeness and cost between the flows. These tradeoffs are important, as the processor developer will likely not want to put the same DV investment into a simple RISC-V microcontroller as for an application processor that will run Linux. The effort involved in each flow is the setup of the DV environment: reference model, comparison mechanism, control functionality in the testbench, test stimuli and functional coverage. Examples will be shown for each of the flows based on current commercial design and open source projects.


Case study: The open verification flow for the CV32E40P open source RISC-V IP Core
•    Speaker:       Kevin McDermott – Imperas Software
•    When:           TBD
Abstract: This case study explores the background, development and implementation of the OpenHW verification environment for CV32E40P known as “core-v-verif”. Since the goal of the project is to support adoption on of an open source IP core, the initial deliverable quality is not the only concern. One attractive aspect of an open source core is the potential for adopters to modify, adapt, or extend the base core features. Thus, the verification plan needs to anticipate the future use case with flexibility built in and clear documentation.

In providing the all details of the OpenHW verification methodology, using industry standard tools, the flow is based on standards that can be shared and further extended. To support the standard SoC methodology this is based on UVM and SystemVerilog test benches. The test plan is based on coverage driven metrics using standard EDA tools. Code snippets of the testbench, Step-And-Compare, coverage, scripting, etc are also provided. Instructions on downloading and running the suite of tests to obtain 100% functional coverage on this RISC-V core will be shown. An attendee will obtain the ability to use the OpenHW verification environment as a baseline to design and verify a custom RISC-V core with their own value-add features.

The flexibility of the open standard ISA of RISC-V is rapidly gaining adoption in SoC designs, yet the verification of a complex processor IP core is a new task for many verification teams. The methodology based on a reliable reference model and Step-and-Compare provides a solution for asynchronous events and debug analysis within a standard UVM SystemVerilog test bench environment. Coverage analysis provides the key metrics for completion, while efficient debug and resolution are essential in achieving the verification schedule targets.


About the RISC-V World Conference China 2021
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