Embedded World 2023 Conference Paper:
The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this also implies the SoC design verification teams will need to address the challenge and complexity of processor verification. This paper outlines open standards and methodologies that assist in both the efficiency and support for the growing community of RISC-V adopters.
Key aspects include:
Test Bench integration standards to support SystemVerilog flows based on traditional SoC techniques extended for RISC-V processor design verification.
Coverage methodologies that support the complexities of process design with asynchronous events including interrupts and debug operations, plus hardware configurations including Out-Of-Order pipelines, vector extensions and custom instructions.
Based on examples from several popular open-source cores this talk will provide guidelines that can help both open-source and commercial projects address the RISC-V functional verification challenge.
Speaker: Jon Taylor – Imperas Software
Co-authors: Mike Thompson – OpenHW Group
Aimee Sutton – Imperas Software
Kevin McDermott – Imperas Software
Simon Davidmann – Imperas Software
Lee Moore – Imperas Software
The slide presentation is also available at this link.