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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

EW23 Paper: Advanced RISC-V Verification Methodology Projects

Embedded World 2023 Conference Paper:

The open standard of RISC-V offers developers new freedoms to explore new design flexibilities and enable innovations with optimized processors. As a design moves from concept to implementation new resources are appearing to help with standards for testbenches, verification IP reuse and coverage analysis. RISC-V offers every SoC team the possibility to design an optimized processor, but this also implies the SoC design verification teams will need to address the challenge and complexity of processor verification. This paper outlines open standards and methodologies that assist in both the efficiency and support for the growing community of RISC-V adopters.
Key aspects include: 
Test Bench integration standards to support SystemVerilog flows based on traditional SoC techniques extended for RISC-V processor design verification.
Coverage methodologies that support the complexities of process design with asynchronous events including interrupts and debug operations, plus hardware configurations including Out-Of-Order pipelines, vector extensions and custom instructions.
Based on examples from several popular open-source cores this talk will provide guidelines that can help both open-source and commercial projects address the RISC-V functional verification challenge.

Speaker:            Jon Taylor – Imperas Software
Co-authors:       Mike Thompson – OpenHW Group
                             Aimee Sutton – Imperas Software
                             Kevin McDermott – Imperas Software
                             Simon Davidmann – Imperas Software
                             Lee Moore – Imperas Software

 

The slide presentation is also available at this link.

View Document

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

ARM TrustZone Platform Modeling Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Bill McSpadden, Principal VLSI Verification Engineer

    Seagate Technology

    The Imperas Golden RISC-V Reference Model helped us find many bugs in our cores.

    However, the RISC-V architectural tests yielded no bugs, which is expected since the architectural tests are a subset of full verification.

  • Allen Baum, Chair of the RISC-V International Architecture Test SIG

    Esperanto Technologies, Inc.

    Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture.

    The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.