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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Rocky Road To Designing Chips In The Cloud

The EDA ecosystem is in the early stages of pivoting to the cloud, but not everything will move there.

Semiconductor Engineering

 

As EDA is moving to the cloud in fits and starts as tool vendors sort out complex financial models and tradeoffs while recognizing a potentially big new opportunity to provide unlimited processing capacity using a pay-as-you-go approach.

By all accounts, a tremendous amount of tire-kicking is happening now as EDA vendors and users delve into the how and why of moving to the cloud for chip design and verification. Not all tools are available in the cloud today, and companies that have their own data centers are likely to continue using them. But EDA in the cloud is adding new opportunities for tools companies, as well as established chipmakers and startups looking to experiment with different architectures and designs….
 

To read the full Semiconductor Engineering article by Ann Steffora Mutschler, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

ARM TrustZone Platform Modeling Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Charlie Hong-Men Su, CTO and Senior VP

    Andes Technology

    The Imperas virtual platform solutions for software development, debug and test, along with their open-source models, comprise an excellent methodology for development of embedded software for SoCs based on V5 AndesCore N25 and NX25 RISC-V processors.

  • Richard Bohn, Engineering Director

    Seagate Technology

    The flexibility of RISC-V helps us address domain-specific requirements with custom processors that go beyond the roadmap of the mainstream IP providers.

    Designing a high-performance RISC-V processor that achieved up to 3x the performance in critical workloads was no small feat. We needed to balance the features and options with the verification implications. The combined solution of Imperas golden reference models and Valtrix STING has helped us to achieve our verification and schedule goals.