Imperas at RISC-V Global Forum, September 3rd 2020

Imperas are co-sponsors with OpenHW including presentations and virtual booth with demonstrations and Q&A discussions with the Imperas team - Presentation recordings now available!

Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced their participation at the RISC-V International Global Forum 2020 as co-sponsors with the OpenHW Group including several talks and virtual booth for demonstrations and live Q&A discussions with the Imperas team.

Presentation ‘Optimizing RISC-V custom instructions with software driven analysis and profiling’

• Speaker:         Simon Davidmann – Imperas Software
• Co-Author:     Duncan Graham – Imperas Software
• When:             Thursday September 3rd, 6:05am PDT / 2:05pm BST

Abstract: One of the attractive features of RISC-V is the ability to add, and with ecosystem support, new optimized instructions and extensions to a processor implementation. At first it appears as simple task to look at opportunities in the application code that could be accelerated with some dedicated new hardware. However, since hardware typically has a much longer life cycle than software, future updates and roadmap needs must be anticipated. Thus, the art of ISA design is using fine grain analysis to accelerate just the key steps while leaving sufficient flexibility to support new software updates and advances. While in multi-core arrays a custom extension can offer a lightweight communication channel between processors. This extends the scope beyond the processor itself into system design and analysis. This talk will illustrate the key profiling and analysis steps for custom extensions. Recording is now available at the RISC-V International YouTube channel.

Presentation ‘Verifying all the flexibility of RISC-V within SoC DV test plans’

• Speaker:         Simon Davidmann – Imperas Software
• Co-Author:     Lee Moore  – Imperas Software
• When:             Thursday September 3rd, 10:20am PDT / 6:20pm BST

Abstract: The open ISA of RISC-V permits may optional configurations and microarchitectural choices plus the options to add custom extensions. This provides designers and system architects freedom to explore optimized designs across almost all market segments. The verification challenge can be addressed with a number of approaches. This talk will give the latest updates to the RISC-V compliance test suite, which was developed with the free riscvOVPsim reference model, the use of an open source instruction stream generator and UVM methodologies based on a SystemVerilog encapsulated RISC-V reference model for step-and-compare verification efficiency. These techniques will be illustrated with results from testing some popular open source cores. This can be a guide to starting your next project with RISC-V, either testing the complete processor or custom extensions. Recording is now available at the RISC-V International YouTube channel.

Presentation ‘CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Core’

• Speaker:         Rick O’Connor – OpenHW Group
• Speaker:         Simon Davidmann – Imperas Software
• Speaker:         Aimee Sutton – Metrics
• When:             Thursday September 3rd, 1:20pm PDT / 9:20pm BST

Abstract: High quality verification is crucial to any HW IP development and in particular for open-source processor cores. Industry quality, coverage driven verification is essential as is leveraging commercial tools, flows and simulators.  These are "must haves" in order for open-source IP to be adopted by leading semiconductor companies for use in high volume SoCs. This talk provides details of the CORE-V Verification Test Bench, an open-source 'step & compare' System Verilog / UVM environment built by the OpenHW Group ecosystem leveraging the Imperas RISC-V Golden Reference Model and the Metrics Cloud-based EDA Platform. Recording is now available at the RISC-V International YouTube channel.

Additional presentations that will feature Imperas technologies by partners & customers include:

Presentation ‘Vector Compliance Testing for RISC-V’

• Speaker:         Hideki Sugimoto – CTO, NSITEXE Inc.
• Speaker:         Koji Adachi – CPU Architect, NSITEXE Inc.
• When:             Thursday September 3rd, 1:45am PDT / 9:45am BST

Abstract: The first step to testing a RISC-V vector instruction implementation is to test compliance to the specification. To do this requires both compliance tests and a reference model. NSITEXE, with its Data Flow Processor (DFP) IP block, required such testing for its implementation of the vector engine. The Imperas RISC-V ISS, riscvOVPsim, is in use as the reference model for the RISC-V Compliance Test Suite (CTS). Imperas has developed a Directed Compliance Test Generator, which achieves over 95% functional instruction coverage with those tests generated. Using the Vector CTS for the NSITEXE configuration has enabled confirmation of compliance with v0.8 of the RISC-V vector specification. This paper will discuss the NSITEXE DFP vector engine implementation, the generation of the Vector Compliance Tests for the NSITEXE configuration and the results of those tests including coverage data. Recording is now available at the RISC-V International YouTube channel.

For more information, or to set up meetings with Imperas during the RISC-V Global Forum at the OpenHW virtual booth, please contact info@imperas.com.

About RISC-V Global Forum
For more information see https://events.linuxfoundation.org/riscv-global-forum/

 

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

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