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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Imperas Participating on Jim Hogan’s Panel at ES Design West, July 9 2019

Imperas at ES Design West 2019 – Panel “Are we Experiencing a Renaissance in Chip Design and EDA?” – July 9 2019

ES Design West 2019

Imperas is participating in Jim Hogan’s panel at ES Design West 2019. The EDA business has evolved with, and has supported chip design challenges of the past, but the end of Moore’s law (EoML) is opening up new opportunities. The panel will consider the implication of the latest in cloud based flexible simulation capacity, increasing design complexing for new application requirements, and the new demands for domain specific processors. This panel will provide deep insights and lively discussions on how this resurgence in chip design starts is leading to a new and significant opportunity for EDA tools.

Panel: "Are we Experiencing a Renaissance in Chip Design and EDA?"

  • Moderator:   Jim Hogan– Managing Partner, Vista Ventures
  • Panelists: 
    • Joe Costello – Chairman of the board, Montana Systems
    • Doug Letcher – President, Metrics
    • Simon Davidmann – President and CEO, Imperas
    • Adnan Hamid – CEO, Breker Verification Systems
    • Raik Brinkmann – President and CEO, One Spin
    • Simon Butler – CEO, Methodics
  • When:  July 9, 2:55pm – 4:00pm
  • Where: TechTALK Theater, South Hall, Moscone Center, San Francisco

Please email info@imperas.com to meet with Imperas at ES Design West!

About ES Design West 2019

ES Design West is co-located with SEMICON West, connecting the entire extended electronics supply chain in one place, at one time. It’s the premier place to re-connect with your contacts and make new ones to drive your business forward. With all-new networking events, “Meet the Experts” Theaters including a dedicated ES Design West theater, ES Design West will help you connect with more qualified customers and partners than ever before.

  • Where: Moscone Convention Center, San Francisco, California, USA
  • When: July 8-11, 2019. 

For more information see http://www.esdesignwest.org

About Imperas

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of their respective holders.

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Custom Instruction Flow Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Han Jin Cho, executive director

    ETRI Korea

    We have seen that virtual platform based methodology can accelerate IoT product development. Imperas OVP models combined with the Imperas embedded software tools, supported by Coontec’s experienced staff, is a great solution for the Korean market.

  • Professor Fernando Gehm Moraes

    Pontifical Catholic University of Rio Grande do Sul, Brazil - PUCRS

    At PUCRS, we use Imperas virtual platforms in projects on multiprocessor SoC modeling, power evaluation, and programmability, as well as computer science graduate program courses on SoCs and research architecture. Our research group (Grupo de Apoio ao Projeto de Hardware, or Hardware Design Support Group), also leverages these tools.