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EW23 RISC-V Theatre: Introduction to RISC-V Processor Verification

Embedded World 2023 - RISC-V Theatre Presentation:

The open RISC-V Instruction Set Architecture (ISA) is enabling a wide range of options on the design side, to completement this a number of options can be applied to the verification tasks, since a basic proof of concept prototype may not need all the quality checks as a high volume or high reliability application. This talk will review the 5 different simulation-based DV flows, ranging from simple signature-based comparisons for architectural validation to advanced ‘step-and-compare’ flows that support asynchronous events and debug.

Speaker:          Larry Lapides – Imperas Software

The video of this presentation is available on YouTube.