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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

5 Takeaways From The RISC-V Summit

From small embedded devices to data centers, the RISC-V ecosystem is growing rapidly.

Codasip article on Semiconductor Engineering

 

After an intense week at the 2022 RISC-V Summit in San Jose, California, I am fueled with energy and positive thoughts. I had plenty of time to reflect on the event, which was unique in many ways. A lot happened in a few days for us at Codasip as well as for the wider RISC-V community, and here are 5 things I will remember from this conference…

To read the full article by Lauranne Choquin, published by Semiconductor Engineering, click here.


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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

RISC-V Custom Instruction Flow Application Note

Comments

  • Dr. Charlie Su, President and CTO

    Andes Technology Corp.

    RISC-V represents the potential for innovation, and it is the implementation of great ideas that are really generating exceptional results.

    To unlock such potentials, Andes provides the AndeSysC™ environment, an extensible and near-cycle accurate SystemC model library for all AndesCore®. SoC architects can use it to construct a SystemC based virtual platform for performance evaluation of critical code segment and hardware/software co-optimization. ACE technology helps users implement custom functions and instructions, and it directly connects to the AndeSysC™ environment. Now with the close integration with the Imperas fast reference models and tools, design teams can embark on architecture exploration with complete application software for the next generation of domain specific devices with a seamless path to ACE implementation.

  • Jingliang (Leo) Wang, Co-chair of the OpenHW Group Verification Task Group

    Futurewei Technologies

    The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores.  The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.

    The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.