x

Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

The RISC-V rundown from DAC 2020

It has been an unusual DAC this year, as the show went virtual due to the Covid-19 pandemic. There was no exhibition floor as such, but there was a comprehensive programme of keynote speeches, presentations, tutorials and panel discussions

Electronics Weekly

There was a lot of activity around RISC-V, including a presentation by Imperas Software (www.imperas.com) entitled ‘What’s Next for RISC-V? Vectors, Verification, and Value-added Extensions’. During the event, the company announced that its RISC-V reference models have been implemented by the OpenHW Group to establish the Core-V processor verification test bench which will validate open source cores for the open source community.
Explaining the alliance’s aim for best practices for hardware and software designers to collaboratively develop open source cores, IP, tools and software, founder and CEO, Rick O’Connor said “The OpenHW Verification Task Group developed and published a [design verification] test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model” …

 

To read the Electronics Weekly article by Caroline Hayes, click here.


##

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

NSITEXE’s RISC-V Success Using ImperasDV and Cadence

Comments

  • Mike Bartley. Founder & CEO

    Test and Verification Solutions Ltd.

    With software now a key deliverable in semiconductor products, our customers increasingly need to develop hardware and software in parallel to hit ever-decreasing market windows, and virtual platforms are a key technique in achieving that. Our partnership with Imperas thus allows T&VS to enhance the solutions we can offer to the market. I am particularly excited by the Imperas fault injection capability which is a key verification technique in the growing safety markets such as automotive.

  • Kazutoshi Wakabayashi, Senior Manager

    Embedded Systems Solution Division, NEC

    OVP is widely used by our customers, who demanded the integration with CyberWorkBench. This integration significantly broadens CWB's HW/SW co-verification support. We were also very impressed with Imperas technical support helping us achieve this integration extremely quickly and efficiently.