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The RISC-V rundown from DAC 2020

It has been an unusual DAC this year, as the show went virtual due to the Covid-19 pandemic. There was no exhibition floor as such, but there was a comprehensive programme of keynote speeches, presentations, tutorials and panel discussions

Electronics Weekly

There was a lot of activity around RISC-V, including a presentation by Imperas Software ( entitled ‘What’s Next for RISC-V? Vectors, Verification, and Value-added Extensions’. During the event, the company announced that its RISC-V reference models have been implemented by the OpenHW Group to establish the Core-V processor verification test bench which will validate open source cores for the open source community.
Explaining the alliance’s aim for best practices for hardware and software designers to collaboratively develop open source cores, IP, tools and software, founder and CEO, Rick O’Connor said “The OpenHW Verification Task Group developed and published a [design verification] test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model” …


To read the Electronics Weekly article by Caroline Hayes, click here.