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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

EW23 Slides: Example of Extending RISC-V for AI/ML Domain Specific Processors

Embedded World 2023 Conference Presentation:

The open standard specification of RISC-V provides the foundation for new approaches to processor design that can be adaptable to address domain specific requirements. To address more complex requirements one approach is to develop multicore processing units than can be optimized for the target workloads. This case study will look at multiprocessor subsystems for AI/ML algorithms for both audio processing and general DSP applications. The design and development of processor IP and multiprocessor systems concurrently offers opportunities to optimize both the hardware and software in parallel, but also requires a new software centric approach to hardware design.
This case study highlights the challenges of verification of custom processor features, development of the multiprocessor communications infrastructure, and software development using full workload analysis to optimize the hardware configurations.
To start the initial software concept development a software simulation approach is used (virtual platform). The starting point is a single CPU model, which is also used for hardware design verification, assembled in a SystemC environment for basic software bring up.
This paper includes a review of the techniques used for verification of the initial RISC-V processor, further extension to the processor subsystem, and multicore software development for real-time audio AI applications.

Speaker:          Larry Lapides – Imperas Software
Co-authors:     Pascal Gouedo – Dolphin Design
                           Damien Le Bars – Dolphin Design
                           Olivier Montfort – Dolphin Design
                           Mike Thompson – OpenHW Group
                           Kevin McDermott – Imperas Software
                           Lee Moore – Imperas Software
                           Aimee Sutton – Imperas Software
 

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

Using OVP Fast Processor Models with OVPsim and other simulators

RISC-V Custom Instruction Flow Application Note

ARM TrustZone Platform Modeling Application Note

Comments

  • Dr. Charlie Su, CTO and EVP

    Andes Technology

    All Andes RISC-V CPU cores are extensible. ACE empowers SoC designers to easily add custom instructions on top of our highly efficient cores to fulfill domain-specific acceleration and bring their SoC performance to the next level.

    Our RISC-V CPU cores are supported by the Imperas simulators already. We are excited to extend our cooperation to enable ACE users to use the Imperas fast simulators so that software engineers can also be engaged with the full development cycle and from the early stage.

  • Chris Jones, VP product marketing

    SiFive, Inc.

    The design freedoms of RISC-V and vector extensions are changing the traditional boundaries between the software and hardware phases of SoC development.

    The Imperas models of the SiFive cores help developers with SoC architectural exploration across the full flexibility of the SiFive Core IP Portfolio, and support early software development, which is a critical factor in validating new AI solutions.