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Revolutionizing Embedded Software Development

EW23 RISC-V Theatre: Introduction to RISC-V Processor Verification

Embedded World 2023 - RISC-V Theatre Presentation:

The open RISC-V Instruction Set Architecture (ISA) is enabling a wide range of options on the design side, to completement this a number of options can be applied to the verification tasks, since a basic proof of concept prototype may not need all the quality checks as a high volume or high reliability application. This talk will review the 5 different simulation-based DV flows, ranging from simple signature-based comparisons for architectural validation to advanced ‘step-and-compare’ flows that support asynchronous events and debug.

Speaker:          Larry Lapides – Imperas Software


The video of this presentation is available on YouTube.

View Document

Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

ARM TrustZone Platform Modeling Application Note

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

RISC-V Custom Instruction Flow Application Note

Comments

  • Hiroyasu Hasegawa, CTO

    hd Lab, Japan

    For our SystemC training courses, we want the attendees to focus on building SystemC models, and how to use those models. By using OVP Fast Processor Models, which work easily in SystemC virtual platforms, students do not have to worry about processor models, and are able to get the most out of our courses. The OVP models work well in our SystemC environment and also with other SystemC tools. We are excited to be able to expand our design service offerings in virtual platforms to our customers.

  • Jingliang (Leo) Wang, Co-chair of the OpenHW Group Verification Task Group

    Futurewei Technologies

    The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores.  The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution.

    The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.