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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

DVCon 2021 Slides on RISC-V Processor Verification: Case Study with NVIDIA Networking

Abstract:

The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors and systems companies. A key question is how to verify the RISC-V processor implementation, especially when developing the RTL and/or adding custom instructions? This paper reports on the techniques used and lessons learned for the verification of a RV64IMACBNSU RISC-V processor by an experienced SoC design team, including the development of the reference model and the SystemVerilog and C encapsulation of the reference model, the step-and-compare flow used included co-debug, and the Specman-based verification environment.

Co-Author:       Adi Maymon – NVIDIA Networking
Co-Author:       Shay Harari – NVIDIA Networking
Co-Author:       Lee Moore – Imperas Software
Co-Author:       Larry Lapides – Imperas Software

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Related Resources

There are many Imperas documents available. Some of them are accessed only from the Imperas User site and are available only to Imperas customers under license.

On the OVPworld website there are many documents that introduce the various APIs and technologies developed by Imperas and made available as part of Open Virtual Platforms. Click here for the OVPworld documentation list.

Publicly available Imperas documents:

RISC-V Processor Verification: ImperasDV with Synopsys VCS and Verdi Application Note

Using OVP Fast Processor Models with OVPsim and other simulators

Using OVP Fast Processor Models with OVPsim and other simulators

Comments

  • Gunar Schirner

    Associate Professor, Northeastern University, Boston, USA

    I find Imperas tools and models invaluable for my research and my course, High Level Design of Hardware Software Systems. My students can now explore and command state-of-the-art prototyping technology for complex systems.

  • Shubhodeep Roy Choudhury, Managing Director & Co-founder

    Valtrix Systems

    As the leading provider of commercial RISC-V Instruction Stream Generators, it is essential for verification standards for test benches and verification IP reuse to evolve.

    Adopting RVVI virtual peripherals provides additional flexibility and efficiency for our flagship verification product STING to target asynchronous event verification, which is essential for quality RISC-V processor functional design verification