RISC-V Summit 2021
This case study explores the background, development and implementation of the OpenHW verification environment for CV32E40P known as “core-v-verif”. Since the goal of the project is to support adoption on of an open-source IP core, the initial deliverable quality is not the only concern. One attractive aspect of an open-source core is the potential for adopters to modify, adapt, or extend the base core features. Thus, the verification plan needs to anticipate the future use case with flexibility built in to the testbench to accommodate future modifications as adopters extend the core features.
Speaker: Simon Davidmann – Imperas Software
Speaker: Lee Moore – Imperas Software
The PDF of the slides used in this talk are available at this link
This RISC-V Summit 2021 presentation can be viewed on the RISC-V YouTube channel here.