Lightning talk: Open-Source RISC-V Cores with Industrial strength verification

RISC-V Summit 2021

Abstract:
This case study explores the background, development and implementation of the OpenHW verification environment for CV32E40P known as “core-v-verif”. Since the goal of the project is to support adoption on of an open-source IP core, the initial deliverable quality is not the only concern. One attractive aspect of an open-source core is the potential for adopters to modify, adapt, or extend the base core features. Thus, the verification plan needs to anticipate the future use case with flexibility built in to the testbench to accommodate future modifications as adopters extend the core features.

Speaker: Simon Davidmann – Imperas Software
Speaker: Lee Moore – Imperas Software

The PDF of the slides used in this talk are available at this link

This RISC-V Summit 2021 presentation can be viewed on the RISC-V YouTube channel here.

Comments

Itai Yarom, VP of Sales and Marketing
MIPS, Inc.
As a developer of leading high-performance RISC-V application processors, verification standards are an important companion to the RISC-V specifications.

Verification standards such as RVVI provide a solid foundation that supports all RISC-V adopters, from basic embedded cores through to complex application processors with multi-cluster, multi-core, multi-threading and out-of-order pipelines.
Don Smith, Vice President Engineering
MIPS, Inc.
At MIPS we are experienced in bringing advanced computing technology, such as hardware multi-threading, to market as applications-class processors.

As part of the strategic move to RISC-V, we fully appreciate the needs, implications and requirements for a high-quality verification solution. The Imperas Reference Model enables lock-step-compare with asynchronous events which is the foundation of our SystemVerilog testbench and verification methodology.

Imperas is now a part of Synopsys