Skip to main content

OpenHW Ecosystem Implements Imperas RISC-V reference models for Coverage Driven Verification of Open Source CORE-V processor IP cores

The OpenHW member-based verification team developing processor design verification test bench to validate open source cores in line with leading industry best practices

OpenHW RISC-V Imperas Reference Model based DV Flow

Oxford, United Kingdom, July 21st, 2020 — Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, today announced that OpenHW Group, the not-for-profit global organization set up to facilitate collaboration between hardware and software designers in the development of open-source IP, has established the CORE-V processor verification test bench using the Imperas RISC-V reference model to deliver quality IP cores to the OpenHW Group ecosystem and the open source hardware community. The OpenHW Group CORE-V Design Verification (DV) test plan is available at together with the UVM testbench GitHub repository at

Processor verification has 4 key parts (1) a DV plan, (2) the tests to run, (3) a device-under-test (DUT) to test, and (4) a reference model for comparison with discrepancy debug and resolution. Within the DV plan a number of metrics are used to record and monitor the overall progress, and in order to ensure a smooth conclusion, one of the key steps is the routine analysis and resolution steps as faults are identified and resolved. Only with a full and complete accounting as all the steps are completed can a DV team collaborate and complete the tasks within a timely and efficient timescale. 

A common processor DV technique to test the complex states and extreme corner cases is to employ a random instruction stream generator, such as the popular Google open source project, RISCV-DV ISG as a test source and can be found on GitHub at By setting up the SystemVerilog test environment to run the tests in a side-by-side configuration, with the DUT and reference model, a step-and-compare methodology can be enabled. This avoids the inefficiencies of logfile based methods and supports direct analysis of any issues found. As a processor has a complex state-space, a step-and-compare approach also supports advanced techniques with dynamic testbenches using UVM (Universal Verification Methodology) and SystemVerilog stimulus/response features.

“The OpenHW Group charter is to deliver high quality processor IP cores for our leading commercial members and open source community adoption,” said Rick O’Connor, Founder and CEO at OpenHW Group. “Central to this goal, the OpenHW Verification Task Group developed and published a DV test plan and implemented an open engineering-in-progress approach as we complete the verification tasks using the Imperas golden RISC-V reference model.”

“Simulation is central to the entire semiconductor design and verification flow, and while a processor is described in Verilog RTL, the industry standard for testbenches is SystemVerilog,” said Steve Richmond, Verification Manager at Silicon Laboratories Inc. and also Co-chair of the OpenHW Group Verification Task Group. “The Verification Task Group is addressing the challenges of processor verification using the Imperas RISC-V golden model encapsulated within our UVM SystemVerilog methodologies.”

“The UVM SystemVerilog testbenches of the OpenHW Verification Task Group, which are publicly available, are well implemented to effectively support multiple RISC-V based 64-bit and 32-bit CPU cores.  The common verification methodology shared by these testbenches does a good job in identifying issues and supporting the analysis and resolution,” said Jingliang (Leo) Wang, Principal Engineer/Lead CPU Design Verification at Futurewei Technologies, Inc. and also Co-chair of the OpenHW Group Verification Task Group. “The Imperas reference model incapsulated within the testbenches is a key component to enable the step-and-compare interactive checking approach for efficient error resolution.”

“As the momentum builds around open source hardware, the OpenHW Group is providing a forum for leading commercial firms to collaborate on the verification of RISC-V processor IP cores,” said Simon Davidmann, CEO at Imperas Software Ltd. “With focused resources and expert methods, the collective group effort is set to achieve tape-out quality for open source cores with full transparency on the methods, test benches and results for state-of-the-art RISC-V processor verification.”
To support the verification work of the OpenHW contributing members, Imperas has developed a SystemVerilog testbench framework which is maintained as part of the library of example platforms. The library of processor models and example platforms are available at, this community-based approach permits users, customers and partners to share and collaborate on projects. The Imperas OVP golden reference model and example step and compare testbench can be found at

About Imperas

Imperas is revolutionizing the development of embedded software and systems and is the leading provider of RISC-V processor models and virtual prototype solutions. Imperas, along with Open Virtual Platforms (OVP), promotes open source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multi-core systems booting SMP Linux. All models are available from Imperas at and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see Follow Imperas on LinkedIntwitter @ImperasSoftware and YouTube.


All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.