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What is next for RISC-V Vectors, Verification, and Value-added Extensions

Imperas presentation on "What is next for RISC-V Vectors, Verification, and Value-added Extensions" by Simon Davidmann, CEO at Imperas, at the RISC-V pavilion during the virtual event for DAC 2020.

This extensive and in-depth update includes an Imperas company overview, and covers the use of virtual platform and simulation throughout the design cycle from early architectural exploration, through processor DV to software development.

 

This DAC presentation can be viewed on the YouTube channel for DAC TV here.

 

Comments

  • Hideki Sugimoto, CTO

    NSITEXE, Inc.

    New design innovations with RISC-V offer great potential in automotive applications, but achieving the extensive quality standards are critical for success.

    The verification requirements to achieve the ASIL D safety requirement level of ISO 26262 with a processor-based design are extensive, however verification IP reuse through standards such as RVVI help improve efficiency and achieve time to market schedules with all the design innovations that RISC-V enables.

  • Philippe Luc, Verification Director

    Codasip

    Imperas are the pioneers in simulation technology and processor verification for RISC-V.

    While processor verification is not a new problem, there are many RISC-V suppliers, with customization and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation. Codasip is very proud of our rigorous approach to verification– using Imperas as an important part of our quality process furthers extend our differentiation. The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors.