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Revolutionizing Embedded Software Development

Imperas is now a part of Synopsys

Webinar on RISC-V and SoC Architecture Exploration - Quick Start demo of early design phase prototypes

Imperas presentation on "RISC-V and SoC Architecture Exploration for AI and ML Many-core Compute Arrays: Quick Start demo of early design phase prototypes" by Kevin McDermott, VP of Marketing at Imperas Software, as part of a webinar together with Andes Technology and UltraSoC Technologies on July 15 2020.

Webinar on the key hardware and software prototyping phase, including demos with example platforms to test multicore processing elements, which are the foundational building blocks of AI Inferencing or ML designs. The Imperas presentation and demonstration highlights "Virtual Platforms as early evaluation & demo boards - Early software development including debug and verification". Includes a Q&A session after the presentations and demonstrations.

This webinar can be viewed on this link. (Requires registration.)

 

Comments

  • Peter Lindskog, Head of Development

    NIRA Dynamics AB, a subsidiary of Audi Electronics Venture GmbH

    In the automotive electronics industry we always need to do more testing of our embedded systems software. Finding that the simulation performance of the Imperas/OVP V850 model was 50 times faster than our previous solution opens up new possibilities for us in software testing, and enables us to increase our test coverage and product reliability.

  • Simon Davidmann, President and CEO

    Imperas Software

    Having partnered with the Wave Computing MIPS engineering team and IP customers over the past decade, our model and simulation technology has enabled MIPS-based devices to be deployed across a broad range of embedded markets.This no-cost MIPSOpenOVPsim instruction set simulator is an ideal start for developers looking to explore the potential of various SoC designs through Wave Computing’s MIPS Open program.