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Webinar on RISC-V and SoC Architecture Exploration for AI an ML ManyCore Compute Arrays

Imperas presentation on "RISC-V and SoC Architecture Exploration for AI and ML Many-Core Compute Arrays" by Kevin McDermott, VP of Marketing at Imperas, as part of a webinar together with Andes Technology and UltraSoC Technologies on May 6 2020.

This webinar covers the latest challenges designers are facing when accelerating AI/ML application with custom SoCs and RISC-V. Artificial Intelligence (AI) and Machine Learning (ML) are among the fastest growing market segments as designers look to optimize domain specific SoC devices to accelerate complex algorithms and applications. While highlighting the latest examples for these applications many of the techniques and insights can equally be applied to any RISC-V based SoC design.

The webinar covers the key SoC design stages of: (1) Architectural exploration: Software driven prototype analysis with virtual platforms. (2) RISC-V core configuration: Optimized features for cores and processor sub-systems. (3) Full on-chip instrumentation: Debug and trace, plus on-chip performance monitors. Concludes with a Q&A session after the presentations and demonstrations.

This webinar can be viewed on this link. (Requires registration.)