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Verifying all the flexibility of RISC-V within SoC DV test plans

Imperas presentation on "Verifying all the flexibility of RISC-V within SoC DV test plans" by Simon Davidmann, CEO at Imperas, at the RISC-V Global Forum during the virtual event on September 3 2020.

One of the attractive features of RISC-V is the ability to add, and with ecosystem support, new optimized instructions and extensions to a processor implementation. At first it appears as simple task to look at opportunities in the application code that could be accelerated with some dedicated new hardware. However, since hardware typically has a much longer life cycle than software, future updates and roadmap needs must be anticipated. Thus, the art of ISA design is using fine grain analysis to accelerate just the key steps while leaving sufficient flexibility to support new software updates and advances.

While in multi-core arrays a custom extension can offer a lightweight communication channel between processors. This extends the scope beyond the processor itself into system design and analysis. This talk illustrates the key profiling and analysis steps for custom extensions.


This RISC-V Global Forum presentation can be viewed on the YouTube channel for RISC-V here.